FAQ for Hardware

• FAQ for ESD
  • 1. Why is the system-level ESD performance degraded when IO pins are near the edge of the PCB?
• FAQ for RF
  • 1. Can the PI circuit for RF be simplified or removed?
  • 2. How does GR551x extend PA or FEM to improve transmission distance?
  • 3. What are the reasons for the low conducted sensitivity and transmit power of the GR5xx?
  • 4. Why are there two first matching capacitors in the GR5331/GR5330 series?
  • 5. Why are there small pF capacitors on the GR533x series VBAT _ RF and GPIO0/1?
  • 6. What about the poor modulation characteristics of GR533x series?
  • 7. What is the reason why the GR533x SK board power or sensitivity cannot be matched to the GR533x different PCB boards using reference design matching parameters?
• FAQ for Minimum System
  • 1. DC-DC 2.2 μH Inductor Selection Requirements?
  • 2. Why does the peripheral interrupt need to access the IO of the AON domain?
  • 3. Can the 32 K external crystal be omitted?
  • 4. How to simplify BOM when GR533x is powered only in SYSLDO mode?
  • 5. Does a 32m, 32.768K crystal require additional external load capacitance?
  • 6. Can the 2.2 μH inductor of the DCDC be replaced with another inductor value?
  • 7. Can the output capacitance of DCDC be increased?
  • 8. What should we pay attention to in DCDC Layout?
  • 9. What does RF Layout need to pay attention to?
  • 10. What should I pay attention to when measuring high-speed signal waveforms such as QSPI?
  • 11. Why can’t some active probes detect the signal transformation of RTC clock signal?
  • 12. What are the 32m, 32.768K crystal PCB Layout requirements?
  • 13. What are the PCB Layout requirements for high-speed signals such as QSPI?
  • 14. Why is the power consumption during sleep high?
  • 15. Are there any precautions when using an external PA?
  • 16. What are the requirements for the LDO power chip when the GR5xx is powered by an LDO?