FAQ for Minimum System

1. DC-DC 2.2 μH Inductor Selection Requirements?

  • 2.The 2 µH power inductor is used in the DC-DC Buck circuit in PSM (Pulse Skip Mode) mode and is critical to the overall DC-DC circuit. Its saturation current needs to be greater than 250 mA, and its DC resistance will affect the power consumption, so the power inductor with large saturation current and small DC resistance is conducive to the safe operation and performance improvement of the system.

2. Why does the peripheral interrupt need to access the IO of the AON domain?

  • When the system enters Sleep or Deep-sleep mode, only the AON _ GPIO is available to wake the system from Sleep/Deep-sleep mode.

  • When the system enters Sleep or Deep-sleep mode, the normal I/O pins remain in the state they were in before going to sleep, and the wake-up function is uninterrupted in the sleep state.

  • The MSIO does not have an interrupt function.

3. Can the 32 K external crystal be omitted?

  • The GR5xx features a low-power, low-frequency clock for extended battery life and a deep-sleep mode. The use of an external RTC ensures tighter timing and higher accuracy.

  • If the system does not need a high-precision low-speed clock, the system can be configured as an internal low-speed clock by software. The precision of the internal low-speed clock is lower than that of the external RTC crystal oscillator.

4. How to simplify BOM when GR533x is powered only in SYSLDO mode?

  • GR533x supports both SYSLDO and DCDC power supply modes. Users can directly delete the 9.1 nH + 2.2 μH inductor material connected to the VSW to simplify the BOM when only the SYSLDO mode is used for power supply. However, the power consumption of the whole machine will increase under the SPA use condition. Refer to the Power Consumption “section of the GR533x Datasheetfor details on the difference between SYSLDO and DCDC power modes.

5. Does a 32m, 32.768K crystal require additional external load capacitance?

  • The adjustable load capacitance is integrated inside the GR5xx series chip, and the load capacitance does not need to be added externally, so the BOM cost can be saved.

6. Can the 2.2 μH inductor of the DCDC be replaced with another inductor value?

  • No. The DCDC on the SoC of GR5xx series chip adopts non-adaptive adjustment mode. The load capacity and ripple of DCDC are strongly related to the inductance value. Increasing the inductance value will lead to insufficient load capacity of DCDC, and decreasing the inductance value will lead to large ripple of DCDC, which will affect RF characteristics.

7. Can the output capacitance of DCDC be increased?

  • No, because the DCDC of GR5xx SoC adopts the Ripple-Base COT DCDC architecture, and the stability of DCDC is strongly related to the ripple. If the output capacitor is increased at will, the ripple of DCDC will be too small, which will affect the stability of the DCDC loop and cause abnormal phenomena such as subharmonics or oscillation of the output voltage of DCDC.

8. What should we pay attention to in DCDC Layout?

  • The 10 μF input capacitance at VBATL and the VSS _ BUCK loop need to be kept to a minimum. The voltage of the input loop is intermittent, so it is necessary to avoid too large loop. The high voltage node radiation at the input of DCDC causes the GND to become dirty, which affects the RF performance, especially the RF Modulation and sensitivity.

  • The DCDC output loop also needs to be minimized because the DCDC operates in PSM mode and the loop has a large di/DT. A large loop will also dirty the GND due to radiation and affect the RF performance.

9. What does RF Layout need to pay attention to?

  • The SoC matching network components in the RF path must be as close as possible to the RF pins of the chip, with the first component placed no more than 1 mm from the RFIO pin; the antenna matching components should be as close to the antenna end as possible.

  • RF devices should be placed on the same layer as much as possible and routed on the surface layer (top or bottom).

  • RF wiring shall be as short and straight as possible. If turning is required due to structural constraints, inverted arc shall be required at the corner, and right-angle wiring and wiring with an included angle of less than 90 ° are prohibited. Ground vias should be added around RF traces.

  • A complete reference ground plane must be guaranteed under the RF traces.

  • The RF trace width should be as close as possible to the pad size of the matching device, with 50 ± 10% Ω impedance control.

10. What should I pay attention to when measuring high-speed signal waveforms such as QSPI?

  • An active probe is required for measurement, and the parasitic capacitance of the active probe is basically less than 2 pF, so that the influence on the signal integrity is small, and the signal quality can be truly observed; The passive probe cannot be used for measurement. The parasitic capacitance of the passive probe is basically between 8 pF and 10 pF, which has a great impact on the high-speed signal. It will cause the signal edge to change slowly and affect the authenticity of the signal.

11. Why can’t some active probes detect the signal transformation of RTC clock signal?

  • The parasitic capacitance of a general active probe is small, but the input impedance is around 1 MΩ. Since the input impedance of the amplifier of the RTC oscillation circuit is also MΩ, when the probe is connected, the RTC drive attenuation is very large due to voltage division, resulting in no RTC oscillation. It is generally recommended to use an active probe with high impedance (10 MΩ +) to measure the RTC.

12. What are the 32m, 32.768K crystal PCB Layout requirements?

  • The crystal should be placed as close to the chip as possible, with a recommended spacing of no more than 4 mm from the corresponding pin of the chip to minimize additional capacitive load on the input pins.

  • Try to avoid other signal lines under the crystal oscillator or around the crystal oscillator trace to avoid crosstalk and interference between the crystal oscillator and other signals.

  • Wiring of the crystal oscillator shall be grounded. If available, a hole can be cut just below the crystal pad to reduce parasitic capacitance.

13. What are the PCB Layout requirements for high-speed signals such as QSPI?

  • For such peripherals with high requirements for speed and timing, the layout position should be as close as possible to the chip according to the structure (the signal Stub is not allowed for short wiring; if conditions permit, it is recommended that the data line and the clock line be of equal length); QSPI traces (up to 3 groups) shall not be crossed with other traces, data lines shall be treated with equal length (equal length error shall be less than ± 50 mil), and CLK traces shall be treated as far as possible.

14. Why is the power consumption during sleep high?

  • High power consumption while sleeping can be caused by incorrectly configured I/O, such as floating I/O, or incorrectly configured I/O pull-up and pulldown. These misconfigurations can result in system leakage. Therefore, it is necessary to correctly configure the state of I/Os before entering sleep. Processing method: when I/O has external pull-up and pull-down or is used as drive output, configuration of pull-up and pull-down is not required; when I/O is not used or works in the input mode without external pull-up, the I/O needs to be configured as internal pull-down.

15. Are there any precautions when using an external PA?

  • If an external PA is used, it is necessary to adapt a specific GPIO to control the TX and RX enablement of the external PA, which are GPIO _ 2 for RX enablement and GPIO _ 3 for TX enablement, respectively.

16. What are the requirements for the LDO power chip when the GR5xx is powered by an LDO?

  • The output current needs to be greater than 300 mA.

  • The typical output voltage is 3.3 V.

  • The LDO has a typical load regulation of 40 mV (Iout = 1 mA to 300 mA).

  • The maximum input voltage of the LDO must be greater than 5.5 V. If not greater than 5.5 V, a small 0.39 Ω to 1 Ω resistor in series with the LDO input is required to prevent thermal power-on overshoot.

  • The quiescent current Iq shall be less than the specification of the product in standby.

  • According to the requirements of product endurance, LDO with low dropout voltage can be selected to increase battery utilization.

  • Special note: When LDO is disabled, if the LDO output pin is grounded, when the peripheral connected to GPIO outputs high level, IO port leakage may occur and the chip may be damaged.