QSPI Application Notes
1. Basic Function Introduction
Each QSPI module provides SPI, Dual SPI, and Quad SPI timing modes.
The number of QSPI modules and main parameters of each chip:
| SoC | QSPI Example | Main Parameters |
|---|---|---|
| GR551x | QSPI0, QSPI1 | Maximum main frequency 32 MHz; APB bus mounted; Memory Map mode not supported; FIFO depth 8x4 bytes |
| GR5525 | QSPI0, QSPI1, QSPI2 | Maximum main frequency 48 MHz; AHB bus mounted; Memory Map mode supported; FIFO depth (16~32)x4 bytes |
| GR5526 | QSPI0, QSPI1, QSPI2 | FIFO depth 8x4 bytes |
| GR533x | None | / |
GR5525 and GR5526 extend Memory Map capability to map NOR Flash and QSPI PSRAM device space to bus address space access. The bus address space for each QSPI instance is as follows (the bus address space and the alias space segment are equivalent, the lowest address all corresponds to the 0 address of the mapped device).
| Chip | QSPI Instance | Memory-Mapped Bus Address Space Segment (recommended for applications) | Alias Space Segment |
|---|---|---|---|
| GR5526 | QSPI0 | [0xC0000000, 0xC4000000) | [0x10000000, 0x14000000) |
| QSPI1 | [0xC4000000, 0xC4000000) | [0x14000000, 0x18000000) | |
| QSPI2 | [0xC8000000, 0xCC000000) | [0x18000000, 0x1C000000) | |
| GR5525 | QSPI0 | [0x10000000, 0x14000000) | |
| QSPI1 | [0x14000000, 0x18000000) | ||
| QSPI2 | [0x18000000, 0x1C000000) |
2. Application Notes
When using Memory Map to access external Flash, please be careful to use address alignment, non-address-aligned data, mis-sequencing may occur.
There are many hardware modules involved in QSPI & SPI timing, the following notes can help users to differentiate them:
| Pan-SPI Timing Modules | Usage Scenarios | Involved Chip Families |
|---|---|---|
| SPIM | SPI Master module, mounted on the APB bus, supports full-duplex mode of operation; used for SPI protocol peripheral drivers for small-sized screens, sensors, etc. | GR551x, GR5525, GR5526, GR533x |
| SPIS | SPI Slave module, mounted on the APB bus, requires the peer to communicate as a Master, fewer usage scenarios | GR551x, GR5525, GR5526, GR533x |
| QSPI | QSPI hardware module, the QSPI module of all the chips can support configuration as SPI, Dual SPI, Quad SPI mode. When configured as SPI, the behavior is similar to the SPIM module. the GR551x's QSPI module is mounted on the APB bus; the GR5525 and GR5526's QSPI modules are mounted on the AHB bus, and their Dual/Quad SPI modes support Memory Map access modes; and the GR533x doesn't have a QSPI module. the QSPI is mainly used for driving the NOR/Nand Flash, PSRAM, display and other peripheral devices | GR551x, GR5525, GR5526 |
| DC | DC is known as Display Controller, note the difference with Direct Current. This hardware module mainly works with the GPU module for display driver control, and supports generating all timing types under the MIPI DBI Type-C protocol family, including SPI, 1-SPI, 3/4-wire SPI, QSPI, and so on. This mode is only available for the GR5526 | GR5526 |
| OSPI | Octual SPI, only for GR5526.The OSPI controller is used as a driver controller for PSRAM devices on the OSPI DDR interface inside the chip, which generates timings for the OSPI DDR timing | GR5526 |
Further understanding of the SPI and Pan-SPI protocols can be found in the article SPI/QSPI Protocol Topic (1) - Introduction to Basic Protocol Characteristics QSPI.
Note the distinction between the concept of QSPI in different application scenarios.
When used to refer to hardware modules, QSPI modules are peripherals of the chip.
When used to denote the concept of timing, QSPI refers to the timing signals consisting of CS, CLK, and D0 to D3.
The principle of using QSPI with DMA:
GR551x: Both QSPI0/QSPI1 can be used with DMA.
GR5525 & GR5526:
When QSPI0/QSPI1/QSPI2 work in Memory Map mode, both DMA0/DMA1 can be used to access the memory space of QSPI0/QSPI1/QSPI2.
When QSPI0/QSPI1/QSPI2 are operating in Register Mode for API interface access, DMA0 can be used with QSPI0/QSPI1 and DMA1 can be used with QSPI1/QSPI2.
When QSPIx and DMA are used together in high throughput rate access scenarios such as Flash, screen, etc., be sure to use channel 0 of the DMA because channel 0 is designed with the deepest FIFO.
When using GR5526 to design screen application products, please note that the screen interface must use the QSPI2 timing interface, because the QSPI2 hardware module and the DC controller’s QSPI timing I/O are the same, so that when driving the screen, you can use both the QSPI2 module and the DC module.
The Memory Map mode of GR5525 & GR5526 supports up to 512 MByte addressing space.
GR5525 & GR5526 use memcpy interface in Memory Map mode, please note that micro-lib should not be used in compilation, as micro-lib will seriously reduce the efficiency of memcpy transfer in QSPI Memory Map mode.
The following recommendations apply to GR5525 & GR5526 QSPI modules:
Generally when moving data in SRAM and QSPI devices working in Memory Map mode, if the amount of data is less than 1 KB, you can prioritize using the If the amount of data is larger than 1 KB, it is recommended to use DMA for moving. If the amount of data is larger than 1 KB, it is recommended to use DMA to move the data. The larger the amount of data, the greater the advantage of DMA.
If you need to use memcpy/memset function to access data in memory mapped mode, please compile the system standard library instead of micrologic library in Keil project. If you need to use memcpy/memset functions to access data in memory-mapped mode, please compile Keil project to use system standard library instead of microlib; the former can activate the bus Burst transfer behavior better and get better access efficiency.
Some QSPI devices need larger Tcsu (CS Setup Delay Time) for timing, otherwise they cannot get correct and stable access data:
If the device supports Clock Mode 3, try to set Clock Mode 3. Compared with Mode 0, Clock Mode 3 has a larger Tcsu.
Tcsu time can be increased by register configuration.
Generally, QSPI PSRAM devices need to release the chip select periodically to complete the self-refresh of the internal data retention circuit, and the maximum chip select time is tCEM, especially for writing data. is tCEM, which needs to be strictly observed especially for write accesses.
For write accesses in memory-mapped mode, tCEM is taken into account in the design and there is no need to pay attention to this parameter.
In register mode, tCEM is considered from the driver layer, but the register mode interface complexity is higher. It is recommended that QSPI PSRAM devices are not used in register mode.
QSPI prefetch mode exists to further improve QSPI read efficiency when performing QSPI read accesses, but this mode can only work with DMA and cannot be turned on during CPU accesses.
GR5525 & GR5526 have differentiated and optimized the FIFOs of each QSPI during the design process, so there is no problem for peripherals to mix and match the QSPIs in general; at the same time, GR5525 & GR5526 have differentiated and optimized the FIFOs of DMA during the design process. In order to utilize the best efficiency of GR5525 & GR5526, the following recommendations are used:
QSPI0 is prioritized for connecting Flash devices and can work with channel 0 of DMA0.
QSPI1 is prioritized for connecting PSRAM devices and can work with channel 0 of DMA0/DMA1.
QSPI2 is prioritized for connecting Display devices and can work with channel 0 of DMA1.
Please prioritize channel 0 of DMA0/DMA1 for high-speed peripherals such as QSPI0/QSPI1/QSPI2, and try not to mix them at the same time.
3. Typical Application Scenarios
3.1 GR5526 supports the use of external flash as firmware cache for OTA upgrade.
Please refer to the following link: