Typical WDT Applications

1. Introduction to GR5xx WDT Basic Functions

  • The chip contains an Always-on Watchdog (AON_WDT) and a System Watchdog. The difference is that the former is in the Always-On domain, using the chip’s internal slow clock, and can continue operating in sleep mode; the latter is in the MCU System domain, using the chip’s high-speed clock, and powers down and stops working in sleep mode. It is recommended to use AON_WDT in application development.

  • The clock source of AON_WDT is the system’s slow clock, with a frequency between 30 kHz and 50 kHz. Our SDK will calibrate (recalculate) the frequency of the slow clock source, so the corresponding reload value may vary.

  • WDT reset function: It counts down from the set 32-bit counter value, and when the counter reaches 0, a system reset will occur.

  • WDT alarm interrupt function: When the counter value decreases to the set alarm value, an alarm interrupt is generated, which can be used to record some information before the watchdog reset. Note that the alarm value of GR551x is only 5 bits, corresponding to a maximum time of less than 1 ms; other chips have an alarm value of 16 bits, corresponding to a maximum time of nearly 2 seconds. Therefore, complex operations cannot be performed during the alarm interrupt of the GR551x, as the interrupt may just respond and the chip will reset.

2. Typical GR5xx WDT Applications

  • How to set the watchdog reset time and alarm time

    • This can be achieved by setting the Counter and alarm_counter member variables of the aon_wdt_init_t structure, and then calling the app_aon_wdt_init API.

    • Note that for the GR551x, the unit of the Counter is Tick, which can be converted to milliseconds (ms) based on the slow clock frequency. For other chips, the unit of the Counter is ms, which can be converted to Ticks based on the slow clock frequency. The unit of alarm_counter is defined similarly. The conversion formula between Tick and ms can be found in the description of the aon_wdt_init_t structure in the header file.

    • For the GR551x, the alarm_counter value is not meaningful in the API interface, and the internal implementation uses the maximum 5-bit alarm_counter value (approximately 1 ms). For other chips, the alarm_counter value is limited by the 16-bit range, and the corresponding value in ms cannot exceed 2000.

    • For more parameter settings and API calls, refer to the “APP AON_WDT Driver” chapter in the GR5xx APP User Driver Manual.

  • How to determine if the system reset is a watchdog reset

    • For the GR551x series, you can determine if a WDT reset has occurred by querying the AON_WDT Reboot Event Flag. However, note that this flag will be cleared in platform_init, so it needs to be read before platform_init.

    • For the GR5525/GR5526/GR533x series, since there is an internal reset reason register, you can determine if it is a WDT reset by querying the reset reason register.

    • For specific methods to determine the reset reason, refer to the forum post “GR55xx Method for Determining Reset Reason”.

  • How to record the context information before a watchdog reset

    • Utilize the WDT’s Alarm interrupt function and set a reasonable Alarm value. When the system is too busy to feed the watchdog, the WDT’s Counter will decrease to the Alarm value, triggering an Alarm interrupt. In the Alarm interrupt, you can record the context information, which helps analyze why the system was too busy to feed the watchdog.

    • The method of recording context information in the WDT Alarm interrupt is the same as recording crash context information in the HardFault_Handler. Users can refer to our SDK’s HardFault_Handler handling method for recording; users can also implement their own recording method in the Alarm interrupt.

    • Note that the time when the GR551x generates an Alarm interrupt is very close to the chip reset time (less than 1 ms), so it may reset before recording. You can try feeding the watchdog in the hal_aon_wdt_alarm_callback function before recording. For more details, refer to the community discussion “How to record the reset reason”.

  • What domains are reset by the watchdog reset The watchdog reset will reset the Bluetooth LE domain, MCU domain, AON domain, etc., with the same effect as a hardware reset and a cold boot.