Minimal System Application Notes

1. Introduction to the GR5xx Minimum System

  • GR551x power supply introduction

    • GR5551x series chips are powered by external power supply through pin VBATL/VBAT_RF, the power supply range is from 2.2 V to 3.8 V.

  • GR5525 Power Supply Introduction

    • GR5525 series chips are powered by external power supply via pin VBATL/VBAT_RF, and the power supply range is from 2.4 V to 3.8 V.

  • Introduction to GR533x Power Supplies

    • GR533x series chips are powered by external power supply through pin VBATL/VBAT_RF, and the power supply range is 2.0 V to 3.63 V. The GR533x series chips support SYSTEMATIC power supply.

    • GR533x supports both SYSLDO and DCDC power supply modes.

  • GR5526 Power Supply Introduction

    • GR5526 series chips are powered by external power supply through pin VBATL/VBAT_RF, and the power supply range is 2.4 V to 4.35 V. The GR533x supports SYSLDO and DCDC power supply modes.

  • The GR5xx series chips are recommended to be powered by a separate LDO/DCDC.

  • GR5xx series chips do not support slow charging of external batteries, and need to use a charger with path management or external circuitry to realize charging path management.

  • GR5xx series chip power-up timing is when CHIP_EN reaches 1 V after power-up, VBATL needs to be higher than its operating voltage, and VDDIO must not be powered up before VBATL.

  • GR5xx series power supply PIN pin introduction

    • VSW: DC-DC switching power supply output pin.

    • VREG: Feedback pin for DC-DC switching power supply output voltage.

    • On-chip DC-DC converter to power the RF analog module with the chip Core LDO. The system turns off this power supply during sleep to save power consumption.

    • VDD_VCO: Internal VCO power supply pin, powered by on-chip DC-DC, connected via external alignment, some chips don’t have this pin, it is enclosed inside the chip with VDD-RF.

    • VDD_AMS: internal analog power supply pin, powered by on-chip DC-DC, connected by external wiring, some chips don’t have this pin, it is enclosed with VDD-RF inside the chip.

    • VDD_RF: Power supply pin for internal RF part, powered by on-chip DC-DC, connected by external wiring.

    • VDD_DIGCORE_1V: Power supply for digital core logic, it is the output pin of Digital LDO, powered by on-chip DC-DC, the system will turn off this power supply during sleep to save power consumption.

    • VDDIO0: IO0 voltage domain power supply input pin, internal Flash power supply pin, can be powered by VIO_LDO_OUT or external regulator, the chip without this PIN pin, its on-chip and VIO_LDO_OUT internal connection.

    • VDDIO1: IO1 voltage domain supply input pin, can be powered by VIO_LDO_OUT or external regulator.

    • VIO_LDO_OUT: IO LDO output pin, supplying power to the internal Flash, or can be externally connected to supply power to VDDIO1.

    • VBATT_RF: RF power supply input pin, connected to VBATL pin.

  • GR5xx clock introduction

    • The system clock source of GR5xx series chips is generated by an external 32 MHz crystal oscillator with a load capacitance of 6 pF to 8 pF, and an internal load capacitor is integrated in the chip.

    • The RTC clock source of the GR5xx series is generated by an external 32.768 kHz crystal, and the load capacitance of the 32.768 kHz crystal must be 6 pF to 9 pF, and the internal load capacitor is integrated.

  • GR5xx burn-in interface introduction

    • The mass production burn-in interfaces of GR5xx series chips are SWDCLK, SWDIO, CLK_TRIM (any GPIO except MSIO), GND, VBAT.

    • If there is an external watchdog chip, you need to reserve the watchdog enable signal or feed dog signal in the burn-in interface.

    • For GR531x series chips, if you need to burn eFuse information, you need one more MSIO7.

2. GR5xx Minimum System Application Notes

  • GR551x VDDIO Voltage Notes

    • GR551x VDDIO1 can be used with 1.8 V to 3.3 V voltage input. When externally inputting the VDDIO1 voltage, be careful not to exceed the input voltage of the power supply Vbatl.

  • GR551x Because VDDIO0 is required to supply power to Flash, the VDDIO0 voltage differs for each model, as listed below:

    • GR5515IGND, GR5515RGBD, GR5515GGBD, GR5513BEND can only use 1.8 V voltage input.

    • GR5515I0ND can only use 3.3 V voltage input.

    • GR5515IENDU, GR5515I0NDA, GR5513BENDU can use 1.8 V to 3.3 V voltage input.

    • When externally inputting the VDDIO0 voltage, be careful not to exceed the input voltage of the power supply Vbatl.

  • GR533x Power Supply Application Notes

    • Peripheral BOM when GR533x uses only SYSLDO power supply can directly remove the 9.1 nH and 2.2 μH inductor materials connected to VSW pin.

    • GR533x can only use SYSLDO power supply mode when using HPA.

    • There are two GR533x IO_LDOs: ANA_IO_LDO and STB_IO_LDO. ANA_IO_LDO has a maximum drive capability of 30 mA, and STB_IO_LDO has a maximum drive capability of 1 mA. switching to STB_IO_LDO at sleep time helps to reduce sleep power consumption, but there are peripheral devices that require the IO_LDO power supply, so be careful! whether the STB_IO_LDO bandwidth capacity meets the peripheral demand.

    • When the GR533x is working as a Slave, do not disconnect the input power supply from the chip VBATL power supply when CHIP_EN is pulled low, otherwise the I/O status of the GR533x may get out of control and be forced to output a high level.

  • GR5526 power supply application notes

    • VDDIO1 supplies power to the internal PSRAM, the corresponding voltages are different for different models as listed below:

      • GR5526VGBIP, GR5526RGNIP can only use 1.8 V voltage input.

      • GR5526VGBI and GR5526RGNI can use 1.8 V to 3.3 V voltage input.

    • VDDIO0 voltage supply requirements

      • 1.8 V to 3.3 V voltage input can be used. Be careful not to exceed the input voltage of the power supply Vbatl when externally inputting the VDDIO0 voltage.

  • GR5525 Power Supply Application Precautions

    • GR5525 series chips are recommended to connect a TVS tube (recommended: µClamp03301ZA) in parallel with the VBATL pin for improving the EOS capability of the system.

    • When GR5525 is working as a Slave, do not disconnect the input power supply from the VBATL power supply of the chip when CHIP_EN is pulled low, otherwise the I/O state of GR5525 may get out of control and be forced to output a high level.

  • Other points to be added